Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes a module in terms of the behavior of a system, the behavior describing the generation and propagation of signals through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
An HDL design can be synthesized to create a logical network list (netlist), which can be implemented as an IC. Prior to implementation, the HDL design can be simulated or emulated to determine whether the design will function as required. Wasted manufacturing costs due to faulty design may thereby be avoided.
Simulation of a circuit design models the circuit design in a computer based environment to determine behavior of circuit design. The simulation uses models of transistors and other components called for by the design of the circuit. Simulation can be used to verify both the IC logic and timing. However, simulation can be very time-consuming and resource intensive since it is software-based.
In emulation, a circuit design and test circuitry are implemented in programmable logic of a programmable IC, such as a field programmable gate array (FPGA) or programmable logic device (PLD). In addition to the circuit design, the programmable logic is configured to implement test circuitry and routing circuitry. The test circuitry provides input stimuli and observes and/or analyzes output signals of the emulated circuit. The routing circuitry routes signals from specific locations (test nodes) of the circuit design to input nodes of the testing circuitry.
The operation of the circuit design can be verified by the test circuitry through analysis of signals sampled from the test nodes. The sampled data is output to a software-based test system that can display results to a user to facilitate debugging. In general, emulation is faster than simulation.
In many cases, programmable logic is utilized for implementation of the circuit design under test (DUT), leaving few, if any, logic resources free for the test and routing circuitry. To reduce the requirement for programmable resources, test circuitry may be reduced in some emulation systems by generating test input and performing analysis of sampled signals externally. For example, the generation of test input and analysis of output may be performed in a software-based testing system that is coupled to the IC. However, the signals from the test nodes in the programmable IC must still be distributed to external pins and a communication interface is needed to transmit data between the programmable IC and external testing system. Due the limited availability of programmable resources or communication bandwidth, it may not be possible to implement routing circuitry to route signals from all of the desired test nodes.
Some previous methods of emulation conduct testing using a limited number of routing circuits to test a selected portion, and/or using a selected subset of desired test nodes of an emulated circuit. Emulation is repeated over a large number of iterations—sampling data from different subset of desired test nodes with each iteration. After emulation is completed, a user or automated software testing program may want to repeat emulation for a different set of desired test nodes based on signals and/or timing data of monitored test nodes.
To configure the programmable IC before each iteration, the circuit design under test, test circuitry, and modified routing circuits are synthesized into a logical network list (netlist) that can be used to configure programmable resources of the programmable IC. The repeated netlist generation and configuration of the programmable IC contributes to a large portion of total emulation runtime.
One or more embodiments may address one or more of the above issues.